Find Available Covid Vaccination Slots: https://cowintrack.com/


Domyhomework123.com - programming homework help. Get your programming homework done with expert homework helper. Trust Writemypaper123.com with your paper and you will never regret it.

Welcome to MyQuestionPoint


Ask Any Question Relative to your Sujbect

Visit: Ask Question


CSE211 : Computer Organization and Architecture Practices Questions for Exam

CSE211 : Computer Organization and Architecture Practices Questions for Exam

Question 1 : 
a)Enable bit plays an important role in decoder expansions. How is this justified in designing?
(a) 3X8 line decoder using two 2X4 line decoders
(b) 5X32 line decoder using four 3X8 and one 2X4 line decoders
b) How we Represent -16 using Fixed Point Signed magnitude ,1s Complement and 2s Complement . 
[Marks 5]

Question 2 : 
a) Discuss the basic logic behind counters i.e. how will you obtain 1000(8) from 0111(7)? How will you implement the same? How many flip flops will be complemented in a 10 bit binary counter to reach the next count after 1001100111 ? 

b) Perform arithmetic operations (+13)+(-45) using 2s Complement . 
[Marks 5]

Question 3 :  a)What will happen if buffer gate in the clock input of the register is removed? What is the role of clear and load signals in designing register with parallel load? 

b) Design of 3 bit counter Using J-K flip flop. 
[Marks 5] 

Question 4 : a) The content of a four bit register is initially 1101. The register is shifted six times to the right with the serial input being 101101. What is the content of the register after each shift? 

b) Draw the block diagram to implement following register transfer statement
yT2+ XT1: R2?R1, R1?R2 [Marks 5] 

Question 5 : a)Register A holds the 8 bit binary 11011001. Determine the B operand and the logic micro operation to be performed in order to change the value in A to 
(a) 01101101 
(b) 11111101.

b) A digital computer has a common bus system for 16 registers of 32 bit each. The bus is constructed with multiplexers.
1. How many selection inputs are there in each multiplexer?
2. What sizes of multiplexers are needed?
3. How many multiplexers are there in the bus? 
[Marks 5]

Question 6 : Draw a Bidirectional 8 bit Shift Register with Truth Table. [Marks 5] 

CSE211 : Computer Organization and Architecture Question Paper for Exam

CSE211 : Computer Organization and Architecture Question Paper for Exam

Question 1. a)Draw the adder- subtractor circuit for input mode M and data inputs A0,A1,A2,A3 & B0,B1,B2,B3. 

b) How can a JK flip flop be converted to T Flip Flop?

c) Design a four bit combinational circuit incrementer and decrementer using full adders(Within One Circuit ).

Question 2 .a) The 8-bit registers AR and CR have the following Values:
AR=11110010
CR=10111001
Determine the 8 bit values in each register after execution of the following sequence of microoperations:
i) AR<-AR+1
ii) AR<-AR-CR
iii)CR<-shr CR 

b) Design a 8 * 1 Multiplexer Using AND gate.

Question 3. a)How are data, address and control buses involved in data transfer to and from memory? Consider a computer system RAM of 1Kb*16 . Calculate the size of data bus and address bus required for the same. 
b)Explain Hardware implementation for Left shift and Right shift using single circuit. 


Question 4. a)What do you mean by Selective complement, Give an example. 

b) Construct a 8 to 1 line multiplexer with 4 to 1 and 2 to 1 line multiplexers.

Question 5. a) Perform arithmetic operations (+15)+(-31) using Signed magnitude ,1s Complement and 2s Complement.

b) Design a 3 to 8 decoder using NAND gates. 

Question 6. Design a common Bus for eight register and Size of each register is 12 bit. Mention details of multiplexers and their inputs. 

CSE211 : Computer Organization and Architecture Mid Term Question Paper | lpu

CSE211 : Computer Organization and Architecture Mid Term Question Paper | lpu

Question  1.
a) Specify the criteria used to classify an instruction into MRI, RRI, or I/O Instruction.

b) What will be the size of data bus and address bus for a memory unit of size 512 x eight (512 words of eight bits each)

c) Draw block diagram to represent the operation P: R1? R2

d) Address Sequencing Capability requires support for 4 various functions. describe them.

e) Determine the logic operand and logic operation that will change the value 1001 to all-zeroes

[2 x five = 10]

Question 2.
a) Design and discuss the working of a circuit that reduces the value of a 4-bit number by one.

b) Represent the design and functioning of Control unit with a block diagram

[6 + four = 10]

Question 3.
a) An 8-bit register R1 contains the value 1000 0001. Determine its value after the subsequent operations:

i. R1? ashl R1
ii. R1? cir R1

b) Design one-stage of an Arithmetic-Logic-Shift unit. discuss its working. Also specify the function table for its operations

[2 + eight = 10]

Question 4.
a) Show the process of monitoring and handling interrupts in the system using a flowchart.

b) What condition determines that the stack is full (FULL ? 1) during the Push operation?

c) describe the purpose, control function, hexa-decimal code and micro-operation sequence corresponding to subsequent computer instructions:

i. ADD
ii. BSA
iii. SKO
iv. CIL
v. HLT

[4 + one + five = 10]

Question 5.
a) Draw block diagram for micro-programmed control organization. Briefly describe the role of every block.

b) Convert the expression { six + ( eight – two ) * four } / three into postfix. DO NOT SOLVE

c) Write 3-address assembly instructions to perform X = ( A + B ) / (A – B)

d) provide at lowest 2 points of differences ranging from every of the subsequent pairs:

i. Immediate Addressing Mode and Implicit Addressing Mode
ii. Interrupt and Subroutine Call

[2 + two + two + four = 10]

CSE211 : Computer Organization and Design Reappear / End Term Exam Question Paper | CSE 211 | LPU

CSE211 : Computer Organization and Design Reappear / End Term Exam Question Paper | CSE 211 | LPU

Computer Organization and Architecture lets you know how exactly each instruction is executed at the micro level. The data flow, timing analysis, memory hierarchy, trade offs between execution cycles, hardware requirements/costs, software-hardware trade-offs can be known.


CSE211 : Computer Organization and Design End Term Exam Question Paper | CSE 211 | LPU

CSE211 : Computer Organization and Design End Term Exam Question Paper | CSE 211 | LPU


Control Unit CPU is divided into Arithmetic Logic Unit (ALU) and Control Unit (CU). The function of control unit is to generate relevant timing and control signals to all operations in the computer. It controls the flow of data between the processor and memory and peripherals.